涓銆丳CIe鍗忚涓庡弬鑰冩椂閽熻姹?/span>
1銆丳CIe鏄粈涔堬紵
PCI Express錛圥eripheral Component Interconnect Express錛夋槸涓縐嶉珮鎬ц兘銆侀珮甯﹀鐨勪覆琛屾葷嚎鏍囧噯錛岀敤浜庤繛鎺ヨ綆楁満鍐呴儴鐨勫悇縐嶇‖浠惰澶囷紝濡傛樉鍗°佸瓨鍌ㄨ澶?SSD)銆佺綉鍗＄瓑銆傚畠鍙栦唬浜嗕紶緇熺殑 PCI 鍜?AGP 鎬葷嚎錛屽茍浠ュ叾楂橀熷害銆佷綆寤惰繜鍜屽己鎵╁睍鎬ф垚涓虹幇浠ｈ綆楁満緋葷粺鐨勬牳蹇冧簰鑱旀妧鏈?/span>
PCIe 鏀寔澶氱閫熺巼鐗堟湰錛屽寘鎷?PCIe 1.0銆丳CIe 2.0銆丳CIe 3.0銆丳CIe 4.0銆丳CIe 5.0鍜孭CIe 6.0錛屾瘡涓増鏈兘鍦ㄥ墠涓浠ｇ殑鍩虹涓婂疄鐜頒簡甯﹀鐨勭炕鍊嶃?/span>
PCIe 6.0宸蹭簬2022騫村彂甯冿紝鍏跺崟閫氶亾閫熺巼鎻愬崌鑷?4 GT/s錛屽茍寮曞叆PAM4璋冨埗鎶鏈紝甯﹀鍐嶆緲誨嶃傚悓鏃訛紝PCIe 6.0榪樺鍔犱簡FEC錛堝墠鍚戠籂閿欙級鍔熻兘錛屼互搴斿楂橀熶紶杈撲腑鐨勪俊鍙瘋“鍑忛棶棰樸?/span>
鍥?錛歅CIE 6.0鍗忚鏍囧噯
2銆丳CIe鍙傝冩椂閽熺殑鍏抽敭浣滅敤
鍦≒CIe緋葷粺涓紝鍙傝冩椂閽燂紙Reference Clock錛夋槸紜繚鏁版嵁浼犺緭鍑嗙‘鎬у拰紼沖畾鎬х殑鏍稿績緇勪歡銆傚叾涓昏浣滅敤鍖呮嫭錛?/span>
路 鍚屾鏁版嵁浼犺緭錛氫負SerDes(涓茶鍣?瑙ｄ覆鍣?鎻愪緵綺懼噯鏃墮挓淇″彿錛岀‘淇濆彂閫佺涓庢帴鏀剁鍚屾銆?/span>
路 闄嶄綆璇爜鐜囷細楂樼簿搴︽椂閽熷噺灝戜俊鍙鋒姈鍔紝闄嶄綆鏁版嵁浼犺緭璇爜鐜?BER)銆?/span>
路 鏀寔澶氳澶囧崗鍚岋細鍦–XL銆丯VMe-oF絳夊鏉傛灦鏋勪腑錛屽弬鑰冩椂閽熼渶瀹炵幇澶氳澶囬棿鐨勭浉浣嶅榻愩?/span>
PCIE鍗忚涓嬬殑鍙傝冩椂閽熷熀鏈負100MHz HCSL杈撳嚭錛岃姹傜‘淇濇暟鎹紶杈撶殑姝ｇ‘鎬у拰紼沖畾鎬э紝瑙ｅ喅鏃墮挓鎶栧姩銆佸亸縐誨拰鍣０闂銆?/span>
闅忕潃PCIe鐗堟湰鐨勫崌綰э紝鍙傝冩椂閽熺殑鎬ц兘瑕佹眰涔熷ぇ騫呮彁楂橈紝涓嬭〃灞曠ず浜嗕笉鍚孭CIe鍗忚鐗堟湰瀵逛簬鍙傝冩椂閽烺MS鎶栧姩鐨勮姹傦細
琛?錛氫笉鍚孭CIe鍗忚鐗堟湰瀵逛簬鍙傝冩椂閽烺MS鎶栧姩鐨勮姹?/span>
浜屻乊XC HCSL杈撳嚭宸垎鏅舵尟錛氭弧瓚砅CIe 5.0鏃墮挓闇姹傜殑鐞嗘兂閫夋嫨
涓哄簲瀵筆CIe 5.0瀵瑰弬鑰冩椂閽熺殑涓ヨ嫑瑕佹眰錛屾帹鑽愪嬌鐢ㄦ壃鍏寸鎶YXC宸垎鎸崱鍣?/span>YSO230LR緋誨垪鍜?/span>YSO231LJ緋誨垪銆傝繖涓ゆ浜у搧鍑熷崜瓚婄殑鎬ц兘鍜屽彲闈犳э紝鎴愪負PCIe 5.0鍙傝冩椂閽熺殑鐞嗘兂閫夋嫨銆?/span>
YXC浜у搧浼樺娍錛?/span>
路 瓚呬綆鎶栧姩錛氱浉浣嶆姈鍔ㄥ彲杈?.05ps(typ.) RMS錛屾弧瓚砅CIe 5.0鐨勪弗鑻涜姹傦紝紜繚淇″彿瀹屾暣鎬э紱
路 楂樼ǔ瀹氬害錛氭婚宸渶浼樺彲杈韭?5ppm @ -40~錒?5鈩冿紱
路 宸垎杈撳嚭錛氭敮鎸丠SCL銆丩VDS銆丩VPECL絳夊縐嶅樊鍒嗚緭鍑猴紱
路 灝忓瀷鍖栵細鎻愪緵2.5*2.0mm绱у噾璁捐錛岄傞厤楂樺瘑搴︿富鏉垮竷灞錛?/span>
路 瀹芥俯鑼冨洿錛氭彁渚?40鈩儈錒?05鈩冦?40鈩儈錒?25鈩冪瓑瀹藉箍鐨勫伐浣滄俯搴﹂夐」銆?/span>